1. Field of the Invention
The invention relates generally to semiconductor power devices. More particularly, this invention relates to new configurations and methods for manufacturing improved power device structures with buried field ring for the field effect transistor (BUF-FET) integrated with cells implanted with hole supply path for sustaining high breakdown voltage while achieving low drain to source resistance RdsA.
2. Description of the Prior Art
Conventional technologies to configure and manufacture high voltage semiconductor power devices are still confronted with difficulties and limitations to further improve the performances due to different tradeoffs. In the vertical semiconductor power devices, there is a tradeoff between the drain to source resistance, i.e., on-state resistance, commonly represented by RdsA (i.e., Rds X Active Area) as a performance characteristic, and the breakdown voltage sustainable of the power device. A commonly recognized relationship between the breakdown voltage (BV) and the RdsA is expressed as: RdsA is directly proportional to (BV)2.5. For the purpose of reducing the RdsA, an epitaxial layer is formed with higher dopant concentration. However, a heavily doped epitaxial layer also reduces the breakdown voltage sustainable by the semiconductor power device.
Several device configurations have been explored in order to resolve the difficulties and limitations caused by these performance tradeoffs. FIG. 1A shows the cross section of a conventional floating island and thick bottom trench oxide metal oxide semiconductor (FITMOS) field effect transistor (FET) implemented with thick bottom oxide in the trench gate and floating P-dopant islands under the trench gate to improve the electrical field shape. The charge compensation of the P-dopant in the floating islands enables the increasing the N-epitaxial doping concentration, thus reduce the RdsA. In addition, the thick bottom oxide in the trench gate lowers the gate to drain coupling, thus lower the gate to drain charge Qgd. The device further has the advantage to support a higher breakdown voltage on both the top epitaxial layer and the lower layer near the floating islands. However, the presence of floating P region causes higher dynamic on resistance during switching.
In U.S. Pat. No. 5,637,898, Baliga discloses a power transistor with a specific goal of providing a high breakdown voltage and low on-state resistance. The power transistor as that shown in FIG. 1B is a vertical field effect transistor in a semiconductor substrate that includes trench having a bottom in the drift region as insulated gate electrode for modulating the conductivity of the channel and drift regions in response to the application of a turn-on gate bias. The insulated gate electrode includes an electrically conductive gate in the trench and an insulating region which lines a sidewall of the trench adjacent the channel and drift regions. The insulating region has a non-uniform cross-sectional area between the trench sidewall and the gate which enhances the forward voltage blocking capability of the transistor by inhibiting the occurrence of high electric field crowding at the bottom of the trench. The thickness of the insulating region is greater along the portion of the sidewall which extends adjacent the drift region and less along the portion of the sidewall which extends adjacent the channel region. The drift region is also non-uniformly doped to have a linearly graded doping profile that decreases in a direction from the drain region to the channel region to provide low on-state resistance. The charge compensation in this device is achieved by the gate electrode. However, the presence of a large gate electrode significantly increases the gate to drain capacitance of this structure, resulting in higher switching losses. In addition, it presents the additional manufacturing complexity of having a linearly graded doping in the drift region.
In U.S. Pat. No. 7,335,944, Banerjee et al. disclose a transistor as that shown in FIG. 1C includes first and second trenches defining a mesa in a semiconductor substrate. First and second field plate members are respectively disposed in the first and second trenches, with each of the first and second field plate members separated from the mesa by a dielectric layer. The mesa includes a plurality of sections, each section having a substantially constant doping concentration gradient, the gradient of one section being at least 10% greater than the gradient of another section, i.e., the doping profile gradient in the drift region varies as a function of the vertical depth of the drift region. Each field plate is electrically connected to the source electrode. In this device, the charge compensation is achieved by the field plate connected to the source. However, the manufacturing of this structure requires complex fabrication processes that include deep trenches and thick liner oxide.
For the above reasons, there is a need to provide new device configurations and new manufacturing methods for the semiconductor power devices reduce the on-state resistance and in the meantime increasing the breakdown voltage sustainable by the power device such that the above discussed difficulties and limitations can be resolved.